CV

Education

M.S. in Integrated Circuit Science and Engineering, Beihang University, 2023.09 - 2026.01
B.S. in Microelectronics, Southwest Jiaotong University, 2019.09 - 2023.06

Work experience

Integrated circuit / hardware acceleration engineer, industry, 2026 - Present

Skills

Programming Language: C, Verilog, Python
Digital IC and FPGA design
- Tools: Design Compiler, VCS, Verdi, ModelSim, SpyGlass, Vivado, Vitis, Quartus
- Application knowledge: AMBA, SoC, RISC-V, cryptographic accelerators
Embedded System
- Hardware: PCB design and Layout with Altium Designer
- Software: MCU platforms such as STM32 and ESP32
Research and engineering interests: ECC, NTT, Montgomery modular multiplication, FPGA/VLSI acceleration, hardware/software co-design, privacy-preserving computing

Publications

Efficient and Agile ECC Acceleration: A Hardware/Software Co-Design with Automated Compilation

Y. Huang and X. Wang, "Efficient and Agile ECC Acceleration: A Hardware/Software Co-Design with Automated Compilation," IEEE International Symposium on Circuits and Systems (ISCAS), 2026. Accepted as poster, Paper ID: 2491.

KD-Finder: A Karatsuba Decomposition Optimization Finder for NTT-Friendly Montgomery Modular Multiplication

Y. Huang, X. Wang, S. Ma, et al., "KD-Finder: A Karatsuba Decomposition Optimization Finder for NTT-Friendly Montgomery Modular Multiplication," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025. DOI: 10.1109/TCAD.2025.3634196.

基于FPGA的高效蒙哥马利模乘器设计

颜震, 黄亦成, 马仕成, 等. "基于FPGA的高效蒙哥马利模乘器设计," 集成电路与嵌入式系统, 2025, 25(4): 1-9. 封面文章.

LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators

Y. Huang, X. Wang, T. Dai, et al., "LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators," 2024 IEEE International Test Conference in Asia (ITC-Asia), Changsha, China, 2024, pp. 1-6. Best Paper Award.

PPGNN: Fast and Accurate Privacy-Preserving Graph Neural Network Inference via Parallel and Pipelined Arithmetic-and-Logic FHE Accelerator

Y. Wei, X. Wang, S. Bian, Y. Huang, W. Zhao, and Y. Jin, "PPGNN: Fast and Accurate Privacy-Preserving Graph Neural Network Inference via Parallel and Pipelined Arithmetic-and-Logic FHE Accelerator," Proceedings of the 61st ACM/IEEE Design Automation Conference (DAC), 2024, Article 273, pp. 1-6. DOI: 10.1145/3649329.3656517.

国密SM4算法CBC模式的高效设计与实现

郝泽钰, 代天傲, 黄亦成, 等. "国密SM4算法CBC模式的高效设计与实现," 计算机研究与发展, 2024, 61(06): 1450-1457.

ESC-NTT: An Elastic, Seamless and Compact Architecture for Multi-Parameter NTT Acceleration

Z. Guan, Y. Zhu, Y. Huang, et al., "ESC-NTT: An Elastic, Seamless and Compact Architecture for Multi-Parameter NTT Acceleration," 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 2024, pp. 1-6.

Yicheng Huang (黄亦成)

CV