Yicheng Huang (黄亦成)

Yicheng Huang (黄亦成)

Integrated circuit and hardware acceleration engineer

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A list of all the posts and pages found on the site. For you robots out there, there is an XML version available for digesting as well.

Pages

Posts

portfolio

publications

ESC-NTT: An Elastic, Seamless and Compact Architecture for Multi-Parameter NTT Acceleration

Published in 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024

ESC-NTT presents a compact and elastic architecture for accelerating number theoretic transform workloads with multiple parameter sets.

Recommended citation: Z. Guan, Y. Zhu, Y. Huang, et al., "ESC-NTT: An Elastic, Seamless and Compact Architecture for Multi-Parameter NTT Acceleration," 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 2024, pp. 1-6.
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国密SM4算法CBC模式的高效设计与实现

Published in 计算机研究与发展, 2024

本文研究国密 SM4 算法 CBC 模式的高效硬件设计与实现。

Recommended citation: 郝泽钰, 代天傲, 黄亦成, 等. "国密SM4算法CBC模式的高效设计与实现," 计算机研究与发展, 2024, 61(06): 1450-1457.
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PPGNN: Fast and Accurate Privacy-Preserving Graph Neural Network Inference via Parallel and Pipelined Arithmetic-and-Logic FHE Accelerator

Published in Proceedings of the 61st ACM/IEEE Design Automation Conference (DAC), 2024

PPGNN accelerates privacy-preserving graph neural network inference with parallel and pipelined arithmetic-and-logic FHE hardware.

Recommended citation: Y. Wei, X. Wang, S. Bian, Y. Huang, W. Zhao, and Y. Jin, "PPGNN: Fast and Accurate Privacy-Preserving Graph Neural Network Inference via Parallel and Pipelined Arithmetic-and-Logic FHE Accelerator," Proceedings of the 61st ACM/IEEE Design Automation Conference (DAC), 2024, Article 273, pp. 1-6. DOI: 10.1145/3649329.3656517.
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KD-Finder: A Karatsuba Decomposition Optimization Finder for NTT-Friendly Montgomery Modular Multiplication

Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025

KD-Finder studies Karatsuba decomposition optimization for NTT-friendly Montgomery modular multiplication, targeting efficient modular arithmetic in cryptographic accelerators.

Recommended citation: Y. Huang, X. Wang, S. Ma, et al., "KD-Finder: A Karatsuba Decomposition Optimization Finder for NTT-Friendly Montgomery Modular Multiplication," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025. DOI: 10.1109/TCAD.2025.3634196.
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talks

ITC-Asia 2024 Presentation: LLP-ECCA

Published:

Presentation for LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators at IEEE ITC-Asia 2024. This work received the Best Paper Award.

teaching