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ECC accelerator and automated compilation

Hardware/software co-design for agile elliptic-curve cryptography acceleration across multiple curves and protocols.

NTT-friendly modular arithmetic accelerators

Montgomery modular multiplication, NTT-friendly arithmetic, and FPGA/VLSI accelerators for privacy-preserving computing.

publications

ESC-NTT: An Elastic, Seamless and Compact Architecture for Multi-Parameter NTT Acceleration

Published in 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024

ESC-NTT presents a compact and elastic architecture for accelerating number theoretic transform workloads with multiple parameter sets.

Recommended citation: Z. Guan, Y. Zhu, Y. Huang, et al., "ESC-NTT: An Elastic, Seamless and Compact Architecture for Multi-Parameter NTT Acceleration," 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 2024, pp. 1-6.
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国密SM4算法CBC模式的高效设计与实现

Published in 计算机研究与发展, 2024

本文研究国密 SM4 算法 CBC 模式的高效硬件设计与实现。

Recommended citation: 郝泽钰, 代天傲, 黄亦成, 等. "国密SM4算法CBC模式的高效设计与实现," 计算机研究与发展, 2024, 61(06): 1450-1457.
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PPGNN: Fast and Accurate Privacy-Preserving Graph Neural Network Inference via Parallel and Pipelined Arithmetic-and-Logic FHE Accelerator

Published in Proceedings of the 61st ACM/IEEE Design Automation Conference (DAC), 2024

PPGNN accelerates privacy-preserving graph neural network inference with parallel and pipelined arithmetic-and-logic FHE hardware.

Recommended citation: Y. Wei, X. Wang, S. Bian, Y. Huang, W. Zhao, and Y. Jin, "PPGNN: Fast and Accurate Privacy-Preserving Graph Neural Network Inference via Parallel and Pipelined Arithmetic-and-Logic FHE Accelerator," Proceedings of the 61st ACM/IEEE Design Automation Conference (DAC), 2024, Article 273, pp. 1-6. DOI: 10.1145/3649329.3656517.
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LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators

Published in 2024 IEEE International Test Conference in Asia (ITC-Asia), 2024

Best Paper Award

Recommended citation: Y. Huang, X. Wang, T. Dai, et al., "LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators," 2024 IEEE International Test Conference in Asia (ITC-Asia), Changsha, China, 2024, pp. 1-6. Best Paper Award.
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基于FPGA的高效蒙哥马利模乘器设计

Published in 集成电路与嵌入式系统, 2025

Cover article

Recommended citation: 颜震, 黄亦成, 马仕成, 等. "基于FPGA的高效蒙哥马利模乘器设计," 集成电路与嵌入式系统, 2025, 25(4): 1-9. 封面文章.
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KD-Finder: A Karatsuba Decomposition Optimization Finder for NTT-Friendly Montgomery Modular Multiplication

Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025

KD-Finder studies Karatsuba decomposition optimization for NTT-friendly Montgomery modular multiplication, targeting efficient modular arithmetic in cryptographic accelerators.

Recommended citation: Y. Huang, X. Wang, S. Ma, et al., "KD-Finder: A Karatsuba Decomposition Optimization Finder for NTT-Friendly Montgomery Modular Multiplication," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025. DOI: 10.1109/TCAD.2025.3634196.
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Efficient and Agile ECC Acceleration: A Hardware/Software Co-Design with Automated Compilation

Published in IEEE International Symposium on Circuits and Systems (ISCAS), 2026

Accepted as poster by IEEE ISCAS 2026. Paper ID: 2491.

Recommended citation: Y. Huang and X. Wang, "Efficient and Agile ECC Acceleration: A Hardware/Software Co-Design with Automated Compilation," IEEE International Symposium on Circuits and Systems (ISCAS), 2026. Accepted as poster, Paper ID: 2491.
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Yicheng Huang (黄亦成)